1. Technical Field of the Invention
The present invention relates generally to high-speed semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to compilable memory instances having self-timed clock circuitry for synchronizing a falling edge of a signal immediately derived from an external master clock to a falling edge of a common node signal driven by a selected bank in a multi-bank memory architecture.
2. Description of Related Art
Design re-use has emerged as a key solution for successfully addressing the time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property ("IP") components--pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system (system-on-chip or SOC). Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that robust performance of memory is pivotal, whether provided in an embedded SOC application or as a stand-alone device. For high speed and high density memories, accordingly, it is desirable that memory access operations are performed without any glitches on the selected wordlines, because such glitches on the wordlines could corrupt data. Further, it is highly desirable for a compiled memory instance to operate with very relaxed requirements on the input clock duty cycle.
One scenario where a wordline (WL) glitch may be encountered is when the falling edge of an external input clock is used to enable the inputting of address information in a multi-bank memory instance, wherein the external clock has a short duty cycle (i.e., short high time). Thus, it is possible that a new address (or an intermediate address if not all predecoders have the same delay) can arrive before the access in a selected memory bank is completed. Consequently, such "early" address signals can glitch the wordline to the new address near the end of the access cycle (which can be a significant problem particularly during a write cycle, where data stored could be corrupted by a false glitch on an unselected WL).
It is therefore highly desirable to have a more or less self-contained timing chain in each bank in a multi-bank memory architecture. Accordingly, a feedback must come from the bank timing chain to a master clock buffer to delay the inputting of the new address and control information into the memory instance until the present memory operation is complete.